Performance enhancement such as improvement in operation speed and reduction in power consumption per single transistor of field-effect transistors for logic devices has been achieved along with miniaturization. However, as the feature size reaches sub-40 nm, it becomes difficult to achieve both performance enhancement such as improvement in operation speed and reduction in power consumption per single transistor. Main causes of the problem include a limitation in on-state current due to increase in leakage current of gate dielectric films or velocity saturation of carriers. Accordingly, as means for solving the problems, usage of high-k gate dielectric films or high-mobility channel such as strained silicon have been considered, and they are currently under development. High-k gate dielectric films are mainly aimed for reducing power consumption of electronic circuits during stand-by state by suppressing tunneling current flowing through the thinned gate insulating film. High-mobility channel is aimed for improving operation speed or reducing power consumption in constant-speed state by increasing output current with the same transistor dimensions.
Further, in addition to the above problems, increase of variability in characteristics among large number of transistors has been getting serious along with miniaturization of transistors. To normally operate all circuits, it is necessary to ensure a voltage margin. Therefore, when the characteristic variation is increased, it becomes difficult to achieve supply voltage reduction having been advanced along with miniaturization of transistors. It makes it difficult to reduce power consumption of a single transistor, and it results in increase in power consumption of a semiconductor chip having more transistors per chip along with miniaturization of transistors. Moreover, when the characteristic variation is large, transistors having large power consumption may eventually largely increase power consumption of the semiconductor chip as a whole. Thus, it is becoming difficult to increase the scale of the integration and functions of the integrated circuits without changing power consumption, while it was possible by scaling transistors on a semiconductor chip with the same area size.
Various techniques capable of dramatically improving performance of semiconductor chips by suppressing characteristic variation have been suggested. For example, Japanese Patent Application Laid-Open Publication No. 2005-251776 (Patent Document 1) discloses an SOI (silicon on insulator) technique. This SOI technique uses a substrate including a very thin SOI layer and a buried insulator (BOX: buried oxide) layer to form a fully depleted SOI (FDSOI: fully depleted silicon on insulator) device, and a substrate bias voltage is applied from a back surface of the BOX layer, so that a threshold voltage (Vth) of the FDSOI device can be changed. According to this SOI technique, for example, when power consumption varies to a larger extent, power consumption can be set back to an appropriate value by adjusting the substrate bias voltage of a semiconductor chip after the FDSOI device is manufactured. It results in improving yield of semiconductor chips. Further, when using a circuit configuration in which a semiconductor chip is divided into a plurality of regions and a substrate bias voltage is automatically adjusted independent with each of the regions, characteristics of all FDSOI devices in the semiconductor chips match well, thereby reducing power consumption of the semiconductor ship.
In addition, as N. Sugii et al., International Electron Devices Meeting 2008 Technical Digest, 2008, p. 249 (Non-Patent Document 1) describes, even when the density of dopant atoms to be introduced to the SOI layer is reduced as compared with that of conventional bulk-type transistors, extremely scaled transistors normally operate. Therefore, variations in characteristics due to statistic variation in the number of dopant atoms that is a problem in extremely scaled transistors can be small. It brings an effect of largely improving stability of circuit operation in circuits in which it is important to have matching of transistor pairs in characteristics of, for example, SRAMs (static random access memories).